1. Field of the Invention
The present invention relates to a data input-processing method applicable to a data input-processing unit, such as a microprocessor or synchronous semiconductor memory device. More particularly, the present invention relates to a multi-clock domain data input-processing unit having a clock signal receiving locked loop (a clock signal receiving synchronous circuit) and the related clock signal applying method.
2. Description of the Related Art
As the operational speed of a central processing unit (CPU) for controlling the operations of a computer system increases, a synchronous dynamic random access memory (hereinafter referred to as SDRAM) that operates synchronously with an external clock is widely used. Specifically, a device known as 2 bit pre-fetch type SDRAM is typically used, since the device can write and read 2 bit data simultaneously. In case of the 2 bit pre-fetch type SDRAM, it is necessary to provide faster clock signals which typically introduce timing skews between a clock signal and a data input signal. In order to correct for such timing skew, a double data rate (hereinafter referred to as DDR) SDRAM has been introduced which captures a data input signal using a data strobe signal and a doubled clock cycle. Standardization of DDR-SDRAM is governed by Joint Electronic Device Engineering Council (JEDEC).
In data input-processing units, such as the DDR-SDRAM, micro-processor and the like, a clock signal, a main signal-receiving clock signal, and data strobe signal are used to input applied input data into the unit. The use of a plurality of clock signals for input operations of the data input-processing unit is defined as a use of a “multi-clock domain” in the following descriptions. When using a multi-clock domain, it is necessary to generate a timing budget as the frequency of the operational clock increases. One technique for generating such a timing budget is to create an internal clock using a phase locked loop (PLL) or delay locked loop (DLL). In a case of the PLL or DLL, consideration should be given to a timing margin in a signal-receiving clock conversion part, wherein one clock signal is converted into another clock signal.
FIG. 1 illustrates a block diagram of a conventional data input-processing unit including a first processing block (hereinafter referred to as memory controller 100) and a second processing block 200. Although such a system typically has a bi-directional data strobe function, wherein first processing block 100 provides data and a data strobe signal to second processing block 200, and the second processing block 200 provides data and a data strobe signal to the first processing block 100, for purposes of brevity in this discussion, only the forward path from first processing block 100 to second processing block 200 will be discussed. It may be understood that the reverse path has a duplicate description.
Data supplied from an input/output processing unit 110 of the memory controller 100 is applied to an input buffer 202 through a first signal-transmitting buffer 112, and a data strobe signal DS supplied from the input/output processing unit 110 is applied to an input buffer 208 through a second signal-transmitting buffer 114. A command signal CMD supplied from the input/output processing unit 110 is applied to an input buffer 212 through a third signal-transmitting buffer 119, and, a clock signal CLK applied from an input node N1 is applied to an input buffer 210. A signal-receiving clock conversion part (CCP) 216, uses a multi-clock domain to input data via first and second latches 204 and 206, respectively. First latch 204 latches data received through the input buffer 202 in response to a data strobe signal received at the strobe terminal through the input buffer 208, and second latch 206 latches data output through an output terminal Q of the first latch 204 in response to a clock signal CLK received at a clock terminal through the input buffer 210. Thus, the data strobe signal DS is used as a clock domain of the first latch 204, and the clock signal CLK is used as a clock domain of the second latch 206.
Next, a timing margin of a signal-receiving clock conversion part CCP will be described with reference to FIG. 2, which illustrates an operational timing diagram of the CCP 216 shown in FIG. 1. As shown in FIG. 2, when the data strobe signal DS is applied through the input buffer 208 (waveform A), a data waveform B is delayed relative to waveform A by time interval T1 at an output terminal of the first latch 204, due to data waveform B being applied to the input buffer 202 in synchronization with a signal-transmitting clock of a signal-transmitting delay locked loop 117. The clocking signal applied to the second latch 206 (waveform C) is typically characterized as having a time delay interval T2, which is due to a mismatch between the paths of the clock signal and the data strobe signal in the second processing block 200. As a result, a standard timing specification, known as tDQSS, which shows a difference in the timing between data strobe signal and clock signal, is obtained by subtracting time intervals T1 and T2 from one period of the clock signal CLK, tCC. For instance, in a DDR-SDRAM using a data strobe signal, a tDQSSmin and tDQSSmax are defined and managed as timing specifications in order to keep the standard tDQSS within a regulated range.
At this time, in order to provide a more thorough understanding about the time interval T1 shown in FIG. 2, the function of a signal-transmitting delay locked loop (T_DLL) will be described with reference to FIGS. 3 and 4.
FIG. 3 illustrates a block diagram of a conventional SDRAM 300 having a signal-transmitting delay locked loop T_DLL 330 and a bi-directional data strobe function. FIG. 4 illustrates a timing diagram of a data output operation of the signal-transmitting delay locked loop shown in FIG. 3.
The output data applied to a data output circuit 340 through a data bus from a SDRAM core 310 is output through an output terminal P1 by synchronizing with an internal clock dll_clk, which is generated by T_DLL 330, rather than an external clock. As shown in FIG. 4, if data (dout) is output by synchronizing with the external clock, a skew is created having a time delay td1. Thus, a new clock needs to be generated that precedes external clock CLK by the time delay td1 in order to compensate for this skew. When T_DLL 330 is adapted to generate internal clock dll_clk to provide this compensation, the output data (dout) supplied to the output terminal of the data output circuit 340 becomes synchronized with the external clock CLK, but without a skew. More specifically, dll_clk is a clock obtained by delaying the external clock CLK by as much as time interval td2. As a result, td2=tCC−td1, and the resultant clock is effectively a clock that precedes CLK by as much as td1.
During a write operation, when write data DIN as shown in FIG. 3 is applied, the data input circuit 320 inputs the write data signal and provides it to a data bus in response to signal-transmitting clock signal CLK and data strobe signal DS. The data provided is thus stored in selected memory cells in the SDRAM core 310.
In order to provide a thorough understanding about detailed operations of the write operational mode and the timing specification of the standard tDQSS in a case of a DDR-SDRAM using a data strobe signal, the write operation of a general DDR-SDRAM will be described with reference to FIGS. 5 and 6.
FIG. 5 illustrates a block diagram of a conventional DDR-SDRAM. FIG. 6 illustrates an operational timing diagram of the write operations of the DDR-SDRAM shown in FIG. 5.
As shown in FIGS. 5 and 6, a DDR-SDRAM is constructed with memory cell arrays 1, 2, word drivers 3, 4, I/O circuits 5A, 6A, write circuits 7, 8, sense amplifier 9, 10, 11, 12, column decoders 13, 14, command decoder 15A, burst counter 16A and column control circuit 17A. As shown in FIG. 6, if a write command is input to a command input port CMD, a data strobe signal DS is applied to I/O circuits 5A, 6A in order to enable the standard tDQSS, which shows the timing difference between data strobe signal DS and clock signal CLK. This timing difference is typically maintained within a regulated range. Assuming that write data D0, D1, D2 and D3 are input as indicated by waveform DQ in FIG. 6 in response to rising and falling edges of the data strobe signal DS, write operation controlling signals WO, W1 are output from column control circuit 17A after a predetermined time interval (for instance, a timing interval of 2 clocks after an input of a command) in response to a read/write command RWCMD output by the command decoder 15A.
On the other hand, when address inputs IA0–IAj are generated in correspondence to addresses A0–Aj designated by CPU, address signals YP0–YPj are output from the burst counter 16A in response to address control signal YALW supplied by the command decoder 15A. After one clock period, an address obtained by adding as much as 2 to the address signals YP0–YPj is output from the burst counter 16A in response to an address control signal NYAL. At this time, data D0 designated by even numbers and data D1 designated by odd numbers are output from data input/output circuits 5A, 6A as data outputs RWBS and RWBSB in response to the write operation control signals W0, W1, respectively. After the data D0, D1 are output from write circuits 7, 8 as write inputs IO and IOB, they are written to memory cells of column selection lines CSL0 and CSL1 designated by addresses YP0, YP1. Then, the data D2, D3 output as write inputs IO and IOB are written to memory cells of column selection lines CSL2 and CSL3 defined by addresses YP0, YP1(+2).
In the DDR-SDRAM described above, data strobe signals and signal-receiving clock signals are all used for write operations. Therefore, it is known that multi-clock domain is used in the DDR-SDRAM. Thus, a signal-receiving clock conversion part shown in the block 200 of FIG. 1 is required in an I/O circuit, such that the standard tDQSS may be managed to remain within its regulated range.
FIGS. 1, 3 and 5 illustrate a conventional scheme having signal-transmitting DLL only for a case of a data transmission. The signal-receiving DLL is typically required at an input unit if a signal-receiving operation requires a higher frequency. Further, it may be necessary to apply a unidirectional data strobe signal and signal-receiving DLL in order to secure timing estimation.
In a case that the aforementioned details are needed for high frequency operations, except the aforementioned factors (time intervals T1 and T2) described in FIG. 2, the timing margin cannot be sufficiently secured in the signal-receiving clock conversion part due to a jitter caused by the signal-receiving DLLs (R_DLL and DS_DLL.) In other words, jitter in the DLLs complicates high frequency operations.
Therefore, when a signal-receiving DLL (R_DLL and DS_DLL) are adapted into a data input part for high frequency operations, there needs to be an improvement in data input-processing unit and a clock signal applying method that can sufficiently secure a timing margin at the signal-receiving clock conversion part.